 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DS5000FP Soft Microprocessor Chip www.dalsemi.com FEATURES 8051-compatible microprocessor adapts to its task - Accesses between 8 and 64 kbytes of nonvolatile SRAM - In-system programming via on-chip serial port - Can modify its own program or data memory - Accesses memory on a separate Bytewide bus Crashproof operation - Maintains all nonvolatile resources for over 10 years - Power-fail Reset - Early Warning Power-fail Interrupt - Watchdog Timer - User-supplied lithium battery backs user SRAM for program/data storage Software security - Executes encrypted programs to prevent observation - Security lock prevents download - Unlocking destroys contents Fully 8051-compatible - 128 bytes scratchpad RAM - Two timer/counters - On-chip serial port - 32 parallel I/O port pins PIN ASSIGNMENT BA11 P0.5/AD5 CE2 P0.6/AD6 BA10 P0.7/AD7 CE1 EA NC BD7 ALE BD6 PSEN BD5 P2.7/A15 BD4 P0.4/AD4 NC NC BA9 P0.3/AD3 BA8 P0.2/AD2 BA13 P0.1/AD1 R/W P0.0/AD0 VCC0 VCC VCC P1.0 BA14 P1.1 BA12 P1.2 BA7 P1.3 NC NC BA6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DS5000FP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P2.6/A14 NC NC BD3 P2.5/A13 BD2 P2.4/A12 BD1 P2.3/A11 BD0 VLI GND GND P2.2/A10 P2.1/A9 P2.0/A8 XTAL1 XTAL2 P3.7/RD P3.6/WR P3.5/T1 NC NC P3.4/T0 DESCRIPTION The DS5000FP Soft Microprocessor Chip is an 8051-compatible processor based on nonvolatile RAM technology. It is substantially more flexible than a standard 8051, yet provides full compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the user can program, then reprogram the microcontroller while in-system. The application software can even change its own operation. This allows frequent software upgrades, adaptive programs, customized systems, etc. In addition, by using NV SRAM, the DS5000FP is ideal for data logging applications. It connects easily to a Dallas Real Time Clock for time stamp and date. The DS5000FP provides the benefits of NV RAM without using I/O resources. It uses a non-multiplexed Byte-wide address and data bus for memory access. This bus can perform all memory access and 1 of 22 112299 P1.4 BA5 P1.5 BA4 P1.6 BA3 P1.7 NC BA2 RST BA1 P3.0/RXD BA0 P3.1/TXD P3.2/INT0 P3.3/INT1 DS5000FP provides decoded chip enables for SRAM. This leaves the 32 I/O port pins free for application use. The DS5000FP uses ordinary SRAM and battery backs the memory contents with a user's external lithium cell. Data is maintained for over 10 years with a very small lithium cell. A DS5000FP also provides crashproof operation in portable systems or systems with unreliable power. These features include the ability to save the operating state, Power-fail Reset, Power-fail Interrupt, and Watchdog Timer. A user loads programs into the DS5000FP via its on-chip Serial Bootstrap Loader. This function supervises the loading of code into NV RAM, validates it, then becomes transparent to the user. Software can be stored in an 8-kbyte or 32-kbyte CMOS SRAM. Using its internal Partitioning, the DS5000FP will divide this common RAM into user programmable code and data segments. This Partition can be selected at program loading time, but can be modified anytime later. It will decode memory access to the SRAM, communicate via its Byte-wide bus and write-protect the memory portion designated as ROM. Combining program and data storage in one device saves board space and cost. The DS5000FP can also access a second 32 kbytes of NV RAM but this area is restricted to data memory. For a user that wants a pre-constructed module using the DS5000FP, RAM, lithium cell, and optional real time clock; the DS2250(T) and DS5000(T) are available and described in separate data sheets. More details are also contained in the User's Guide section of the Secure Microcontroller Data Book. ORDERING INFORMATION The following devices are available as standard products from Dallas Semiconductor: PART # DS5000FP-16 DESCRIPTION 80-pin QFP, Max. clock speed 16 MHz, 0 to 70C operation Operating information is contained in the User's Guide section of the Secure Microcontroller Data Book. This data sheet provides ordering information, pin-out, and electrical specifications. 2 of 22 DS5000FP DS5000FP BLOCK DIAGRAM Figure 1 3 of 22 DS5000FP PIN DESCRIPTION PIN DESCRIPTION 15, 17, 19, P1.0 - P1.7. General purpose I/O Port 1. 21, 25, 27, 29, 31 34 36 38 39 40 41 44 45 46 47, 48 52, 53 RST - Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally so this pin can be left unconnected if not used. P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on board UART. This pin should not be connected directly to a PC COM port. P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on board UART. This pin should not be connected directly to a PC COM port. P3.2 INT0 . General purpose I/O port pin 3.2. Also serves as the active low External Interrupt 0. P3.3 INT1 . General purpose I/O port pin 3.3. Also serves as the active low External Interrupt 1. P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input. P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input. P3.6 WR . General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation. P3.7 RD . General purpose I/O port pin. Also serves as the read strobe for Expanded bus operation. XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output. GND. Logic ground. 49, 50, 51, P2.0-P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address 56, 58, 60, bus. 64, 66 68 PSEN - Program Store Enable. This active low signal is used to enable an external program memory when using the Expanded bus. It is normally an output and should be unconnected if not used. PSEN is also used to invoke the Bootstrap Loader. At this time, PSEN will be pulled down externally. This should only be done once the DS5000FP is already in a reset state. The device that pulls down should be open drain since it must not interfere with PSEN under normal operation. 70 ALE - Address Latch Enable. Used to de-multiplex the multiplexed Expanded Address/Data bus on Port 0. This pin is normally connected to the clock input on a '373 type transparent latch. When using a parallel programmer, this pin also assumes the PROG function for programming pulses. - External Access. This pin forces the DS5000FP to behave like an 8031. No internal memory (or clock) will be available when this pin is at a logic low. Since this pin is pulled down internally, it should be connected to +5V to use NV RAM. In a parallel programmer, this pin also serves as VPP for super voltage pulses. EA 73 4 of 22 DS5000FP PIN DESCRIPTION 11, 9, 7, 5, P0.0-P0.7. General purpose I/O Port 0. This port is open-drain and can not drive a logic 1. 1, 79, 77, It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data bus. 75 When used in this mode, it does not require pullups. 13, 14 16, 8, 18, 80, 76, 4, 6, 20, 24, 26, 28, 30, 33, 35, 37 VCC - +5V BA14-0. Byte-wide Address bus bits 14-0. This 15 bit bus is combined with the nonmultiplexed data bus (BD7-0) to access NV SRAM. Decoding is performed on CE1 and CE2 . Read/write access is controlled by R/ W . BA14-0 connect directly to an 8k or 32k SRAM. If an 8k RAM is used, BA13 and BA14 will be unconnected. Note BA13 and BA14 are inverted from the true logical address. Also note that BA14 is lithium backed. 71, 69, 67, BD7-0. Byte-wide Data bus bits 7-0. This 8-bit bi-directional bus is combined with the 65, 61, 59, non-multiplexed address bus (BA14-0) to access NV SRAM. Decoding is performed on 57, 55 CE1 and CE2 . Read/write access is controlled by R/W. BD7-0 connect directly to an 8k or 32k SRAM, and optionally to a Real-time Clock. 10 R/W - Read/Write. This signal provides the write enable to the SRAMs on the Byte-wide bus. It is controlled by the memory map and Partition. The blocks selected as Program (ROM) will be write protected. CE1 - Chip Enable 1. This is the primary decoded chip enable for memory access on the Byte-wide bus. It connects to the chip enable input of one SRAM. CE1 is lithium backed. It will remain in a logic high inactive state when VCC falls below VLI. CE2 - Chip Enable 2. This chip enable is provided to bank switch to a second block of 32k bytes of nonvolatile data memory. It connects to the chip enable input of one SRAM or one lithium-backed peripheral such a DS1283 clock. CE2 is lithium backed. It will remain in a logic high inactive state when VCC falls below VLI. 74 78 12 VCCO - VCC Output. This is switched between VCC and VLI by internal circuits based on the level of VCC. When power is above the lithium input, power will be drawn from VCC. The lithium cell remains isolated from a load. When VCC is below VLI, the VCCO switches to the VLI source. VCCO is connected to the VCC pin of an SRAM. VLIL - Lithium Voltage Input. Connect to a lithium cell greater than VLImin and no greater than VLImax as shown in the electrical specifications. Nominal value is +3V. 54 2, 3, 22, NC do not connect. 23, 32, 42, 43, 62, 63, 72 INSTRUCTION SET The DS5000FP executes an instruction set that is object code compatible with the industry standard 8051 microcontroller. As a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the DS5000FP. A complete description of the instruction set and operation are provided in the User's Guide section of the Secure Microcontroller Data Book. Also note that the DS5000FP is embodied in the DS5000(T) and DS2250(T) modules. The DS5000(T) combines the DS5000FP with one SRAM of either 8 or 32 kbytes and a lithium cell. An optional Real Time Clock is also available in the DS5000T. This is packaged in a 40-pin DIP module. The DS2250(T) 5 of 22 DS5000FP is an identical function in a SIMM form factor. It also offers the option of a second 32k SRAM mapped as data on Chip Enable 2. MEMORY ORGANIZATION Figure 2 illustrates the memory map accessed by the DS5000FP. The entire 64k of program and 64k of data is available. The DS5000FP maps 32k of this space into the SRAM connected to the Byte-wide bus. This is the area from 0000h to 7FFFh (32k) and is reached via CE1 . Any area not mapped into the NV RAM is reached via the Expanded bus on Ports 0 & 2. Selecting CE2 provides another 32k of potential data storage. When CE2 is used, no data is available on the ports. The memory map is covered in detail in the User's Guide section of the Secure Microcontroller Data Book. Figure 3 illustrates a typical memory connection for a system using 8k bytes of SRAM. Figure 4 shows a similar system with 32 kbytes. The Byte-wide Address bus connects to the SRAM address lines. The bidirectional Byte-wide data bus connects the data I/O lines of the SRAM. CE1 provides the chip enable and R/ W is the write enable. An additional RAM could be connected to CE2 , with common connections for R/ W , BA14-0, and BD7-0. 6 of 22 DS5000FP POWER MANAGEMENT The DS5000FP monitors power to provide Power-fail Reset, early warning Power-fail Interrupt, and switch-over to lithium backup. It uses the Lithium cell at VLI as a reference in determining the switch points. These are called VPFW, VCCMIN, and VLI respectively. When VCC drops below VPFW, the DS5000FP will perform an interrupt vector to location 2Bh if the power-fail warning was enabled. Full processor operation continues regardless. When power falls further to VCCMIN, the DS5000FP invokes a reset state. No further code execution will be performed unless power rises back above VCCMIN. CE1 , CE2 , R/ W go to an inactive (logic 1) state. Any address lines that are high (due to encryption) will follow VCC, except for BA14, which is lithium backed. VCC is still the power source at this time. When VCC drops further to below VLI, internal circuitry will switch to the lithium cell for power. The majority of internal circuits will be disabled and the remaining nonvolatile states will be retained. Any devices connected to VCCO will be powered by the lithium cell at this time. VCCO will be at the lithium battery voltage less a diode drop. This drop will vary depending on the load. Low leakage SRAMs should be used for this reason. When a module is used, the lithium cell is selected by Dallas so absolute specifications are provided for the switch thresholds. When using the DS5000FP, the user must select the appropriate battery. The following formulas apply to the switch function. VPFW = 1.45 * VLI VCCMIN = 1.40 * VLI VLI Switch = 1.0 * VLI MEMORY MAP OF THE DS5000FP Figure 2 7 of 22 DS5000FP DS5000FP CONNECTION TO 8k X 8 SRAM Figure 3 DS5000FP CONNECTION TO 32k X 8 SRAM Figure 4 8 of 22 DS5000FP ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * -0.3V to +7.0V 0C to 70C -40C to +70C 260C for 10 seconds This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 9 of 22 DS5000FP DC CHARACTERISTICS PARAMETER Input Low Voltage Input High Voltage Input High Voltage RST, XTAL1 Output Low Voltage @ IOL=1.6 mA (Ports 1, 2, 3) Output Low Voltage @ IOL=3.2 mA (Ports 0, ALE, PSEN , BA14-0, BD7-0, R/ W , CE 1-2) Output High Voltage @ IOH= -80 A (Ports 1, 2, 3) Output High Voltage @ IOH=-400 A (Ports 0, ALE, PSEN , BA14-0, BD7-0, R/ W , CE 1-2) Input Low Current VIN = 0.45V (Ports 1, 2, 3) Transition Current; 1 to 0 VIN = 2.0V (Ports 1, 2, 3) Input Leakage Current 0.45 < VIN < VCC (Port 0) RST, EA Pulldown Resistor Stop Mode Current Power-Fail Warning Voltage Minimum Operating Voltage Lithium Supply Voltage Programming Supply Voltage (Parallel Program Mode) Program Supply Current Operating Current @ 16 MHz Idle Mode Current @ 12 MHz Output Supply Voltage Output Supply Voltage (Battery-backed mode) Output Supply Current @ VCCO = VCC-0.3V Battery-Backed Quiescent Current SYMBOL VIL VIH1 VIH2 VOL1 VOL2 MIN -0.3 2.0 3.5 (tA=0C to70C; VCC=5V 5%) TYP MAX 0.8 VCC+0.3 VCC+0.3 0.15 0.15 0.45 0.45 UNITS V V V V V 1 NOTES 1 1 1 VOH1 VOH2 2.4 2.4 4.8 4.8 V V 1 1 IIL ITL IL RRE ISM VPFW VCCmin VLI VPP IPP ICC IIDLE VCCO1 VCCO2 ICCO1 ILI VCC-0.3 VLI-0.65 VLI-0.5 80 5 4.15 4.05 2.9 12.5 15 4.6 4.5 40 -50 -500 10 125 80 4.75 4.65 3.3 13 20 36 6.2 A A A k A V V V V mA mA mA V V mA 2 3 1 8 2 7 4 1, 6 1, 6 1 1 75 nA 10 of 22 DS5000FP AC CHARACTERISTICS: EXPANDED BUS MODE TIMING SPECIFICATIONS # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 PARAMETER Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instr. In ALE Low to PSEN Low PSEN PSEN (tA=0C to70C; VCC=5V 5%) SYMBOL 1/tCLK tALPW tAVALL tAVAAV MIN 1.0 2tCLK -40 tCLK -40 tCLK -35 4tCLK -150 4tCLK -90 tCLK -25 3tCLK -35 3tCLK -150 3tCLK -90 0 tCLK -20 tCLK -8 5tCLK -150 5tCLK -90 0 6tCLK -100 6tCLK -100 5tCLK -165 5tCLK -105 0 2tCLK -70 8CLK -150 8tCLK -90 9tCLK -165 9tCLK -105 3tCLK -50 4tCLK -130 tCLK -60 7tCLK -150 7tCLK -90 tCLK -50 0 tCLK -40 tCLK +50 3tCLK +50 MAX 16 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns @ 12 MHz @ 16 MHz tALLVI tALLPSL tPSPW Pulse Width Low to Valid Instr. In @ 12 MHz @ 16 MHz tPSLVI tPSIV tPSIX tPSAV tAVVI tPSLAZ tRDPW tWRPW Input Instr. Hold after PSEN Going High Input Instr. Float after PSEN Going High Address Hold after PSEN Going High Address Valid to Valid Instr. In @ 12 MHz @ 16 MHz PSEN RD Low to Address Float Pulse Width Pulse Width Low to Valid Data In @ 12 MHz @ 16 MHz WR RD tRDLDV tRDHDV tRDHDZ Data Hold after RD High Data Float after RD High ALE Low to Valid Data In Valid Addr. to Valid Data In ALE Low to RD or WR Low Address Valid to RD or WR Low Data Valid to WR Going Low Data Valid to WR High Data Valid after WR High RD RD @ 12 MHz @ 16 MHz @ 12 MHz @ 16 MHz tALLVD tAVDV tALLRDL tAVRDL tDVWRL tDVWRH tWRHDV tRDLAZ tRDHALH @ 12 MHz @ 16 MHz Low to Address Float or WR High to ALE High 11 of 22 DS5000FP EXPANDED PROGRAM MEMORY READ CYCLE EXPANDED DATA MEMORY READ CYCLE 12 of 22 DS5000FP EXPANDED DATA MEMORY WRITE CYCLE EXTERNAL CLOCK TIMING 13 of 22 DS5000FP AC CHARACTERISTICS (cont'd) EXTERNAL CLOCK DRIVE # 28 29 30 31 PARAMETER External Clock High Time External Clock Low Time External Clock Rise Time External Clock Fall Time @ 12 MHz @ 16 MHz @ 12 MHz @ 16 MHz @ 12 MHz @ 16 MHz @ 12 MHz @ 16 MHz SYMBOL tCLKHPW tCLKLPW tCLKR tCLKF (tA=0C to70C; VCC=5V 5%) MIN 20 15 20 15 20 15 20 15 MAX UNITS ns ns ns ns ns ns ns ns AC CHARACTERISTICS (cont'd) SERIAL PORT TIMING - MODE 0 # 35 36 37 38 39 PARAMETER Serial Port Cycle Time Output Data Setup to Rising Clock Edge Output Data Hold after Rising Clock Edge Clock Rising Edge to Input Data Valid Input Data Hold after Rising Clock Edge SYMBOL tSPCLK tDOCH tCHDO tCHDV tCHDIV (tA=0C to70C; VCC=5V 5%) MIN 12tCLK 10tCLK -133 2tCLK -117 10tCLK -133 0 MAX UNITS s ns ns ns ns SERIAL PORT TIMING - MODE 0 14 of 22 DS5000FP AC CHARACTERISTICS (cont'd) POWER CYCLING TIMING # 32 33 34 PARAMETER Slew Rate from VCCmin to VLImax Crystal Startup Time Power-On Reset Delay SYMBOL tF tCSU tPOR (tA=0C to70C; VCC=5V 5%) MIN 40 MAX (note 5) 21504 tCLK UNITS s POWER CYCLE TIMING 15 of 22 DS5000FP AC CHARACTERISTICS (cont'd) PARALLEL PROGRAM LOAD TIMING # 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 PARAMETER Oscillator Frequency Address Setup to PROG Low Address Hold after PROG High Data Setup to PROG Low Data Hold after PROG High P2.7, 2.6, 2.5 Setup to VPP VPP Setup to PROG Low VPP Hold after PROG Low PROG (tA=0C to70C; VCC=5V 5%) SYMBOL 1/tCLK tAVPRL tPRHAV tDVPRL tPRHDV tP27HVP tVPHPRL tPRHVPL tPRW tAVDV tDVP27L tP27HDZ tPORPV tRAVPH tVPPPC tVFT 0 21504 1200 1200 48 2400* MIN 1.0 0 0 0 0 0 0 0 2400 48 1800* 48 1800* 48 1800* tCLK tCLK tCLK tCLK tCLK tCLK tCLK tCLK MAX 12.0 UNITS MHz Width Low Data Output from Address Valid Data Output from P2.7 Low Data Float after P2.7 High Delay to Reset/ PSEN Active after Power On Reset/ PSEN Active (or Verify Inactive) to VPP High VPP Inactive (Between Program Cycles) Verify Active Time * Second set of numbers refers to expanded memory programming up to 32k bytes. 16 of 22 DS5000FP PARALLEL PROGRAM LOAD TIMING CAPACITANCE PARAMETER Output Capacitance Input Capacitance SYMBOL CO CI MIN (test frequency=1MHz; tA=25C) TYP MAX 10 10 UNITS pF pF NOTES 17 of 22 DS5000FP BYTE-WIDE ADDRESS/DATA BUS TIMING AC CHARACTERISTICS # 56 57 58 59 60 61 62 63 64 65 66 67 68 69 PARAMETER Delay to Embedded Address Valid from CE1 Low During Opcode Fetch CE1 (tA=0C to70C; VCC=5V 5%) MIN MAX 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tCE1LPA tCEPW tCE1HPA tOVCE1H tCE1HOV tCEHDA tCELDA tDACEH tCEHDV tAVRWL tRWLDV tCEHDV tRWHDV tRWLPW or CE2 Pulse Width 4tCLK-15 2tCLK-20 1tCLK+40 10 4tCLK-30 4tCLK-25 1tCLK+40 10 3tCLK-35 20 1tCLK-15 0 6tCLK-20 Embedded Address Hold after CE1 High During Opcode Fetch Embedded Data Setup to CE1 High During Opcode Fetch Embedded Data Hold after CE1 High During Opcode Fetch Embedded Address Hold after CE1 or CE2 High During MOVX Delay from Embedded Address Valid to CE1 or CE2 Low During MOVX Embedded Data Hold Setup to CE1 or CE2 High During MOVX (read) Embedded Data Hold after CE1 or CE2 High During MOVX (read) Embedded Address Valid to R/ W Active During MOVX (write) Delay from R/ W Low to Valid Data Out During MOVX (write) Valid Data Out Hold Time from CE1 or CE2 High Valid Data Out Hold Time from R/ W High Write Pulse Width (R/ W low time) 18 of 22 DS5000FP BYTE-WIDE ADDRESS/DATA BUS OPCODE FETCH CYCLE BYTE-WIDE ADDRESS/DATA BUS OPCODE FETCH WITH DATA MEMORY READ 19 of 22 DS5000FP BYTE-WIDE ADDRESS/DATA BUS OPCODE FETCH WITH DATA MEMORY WRITE NOTES: 1. All voltages are referenced to ground. 2. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF=10 ns, VIL= 0.5V; XTAL2 disconnected; EA = RST = PORT0 = VCC. 3. Idle mode ICC is measured with all output pins disconnected; XTAL1 driven at 12 MHz with tCLKR, tCLKF=10 ns, VIL= 0.5V; XTAL2 disconnected; EA = PORT0 = VCC, RST = VSS. 4. Stop mode ICC is measured with all output pins disconnected; EA = PORT0 = VCC; XTAL2 not connected; RST = VSS. 5. Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the crystal vendor for the worst-case spec on this time. 6. Assumes VLI=3.3V maximum. 7. ILI is the current drawn from VLI when VCC=0V and VCCO is disconnected. 8. I CCO=10 A. 20 of 22 DS5000FP DS5000FP CMOS MICROPROCESSOR DIM A A1 A2 B C D D1 E E1 e L MILLIMETERS MIN 0.25 2.55 0.30 0.13 23.70 19.90 17.40 13.90 MAX 3.15 2.87 0.50 0.23 24.10 20.10 18.10 14.10 0.80 BSC 0.65 0.95 56-G4005-001 21 of 22 DS5000FP DATA SHEET REVISION SUMMARY The following represent the key differences between 07/27/95 and 07/24/96/96 version of the DS5000FP data sheet. Please review this summary carefully. 1. Add VCCO2 Minimum Specification (PCN F62501). 2. Add embedded bus DC specifications. 3. Update mechanical specifications. 22 of 22 |
Price & Availability of DS5000FP
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |